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TSA1002
10-BIT, 50MSPS, 50mW A/D CONVERTER
s 10-bit A/D converter in deep submicron s s s s s s s s
CMOS technology Single supply voltage: 2.5V Input range: 2Vpp differential 50Msps sampling frequency Ultra low power consumption: 50mW @ 50Msps ENOB=9.4 @ Fs=50Msps, Fin=15MHz SFDR typically up to 72dB @ Fs=50Msps, Fin=5MHz Built-in reference voltage with external bias capability STMicroelectronics 8, 10, 12 and 14-bits ADC pinout compatibility ORDER CODE
Part Number TSA1002CF TSA1002CFT TSA1002IF TSA1002IFT EVAL1002/AA Temperature Range 0C to +70C 0C to +70C -40C to +85C -40C to +85C Package TQFP48 TQFP48 TQFP48 TQFP48 Conditioning Tray Tape & Reel Tray Tape & Reel Marking SA1002C SA1002C SA1002I SA1002I
Evaluation board
PIN CONNECTIONS (top view)
DESCRIPTION The TSA1002 is a 10-bit, 50Msps sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1002 is based on a pipeline structure and digital error correction to provide excellent static linearity and guarantee 9.4 effective bits at Fs=50Msps, and Fin=15MHz. A voltage reference is integrated in the circuit to simplify the design and minimize external components. It is nevertheless possible to use the circuit with an external reference. Especially designed for high speed, low power applications, the TSA1002 only dissipates 50mW at 50Msps. A tri-state capability, available on the output buffers, enables to address several slave ADCs by a unique master. The output data can be coded into two different formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA1002 is available in commercial (0 to +70C) and extended (-40 to +85C) temperature range, in a small 48 pins TQFP package. APPLICATIONS
index corner
48 1 2 3 4 5 6 7 8 9 10 11 12 13
AGND
AVCC
VCCB
GNDB
47 46
AVCC
VCCB
45
DFSB
44 43
OEB
NC
42
NC
NC
37 36 NC 35 NC 34 NC 33 D0 (LSB) 32 D1 31 D2
DR
41
40
39
38
IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC
TSA1002
30 D3 29 D4 28 D5 27 D6 26 D7 25 D8
14 15
16
17
18 19
20
21
22
23
24
DGND
DVCC
DVCC
DGND
CLK
DGND
NC
GNDB
GNDB
VCCB
OR
D9 (MSB)
PACKAGE
7 x 7 mm TQFP48
s s s s s
Medical imaging and ultrasound Portable instrumentation Cable Modem Receivers High resolution fax and scanners High speed DSP interface
October 2000
1/19
TSA1002
ABSOLUTE MAXIMUM RATINGS
Symbol AVCC DVCC VCCB IDout Tstg ESD Analog Supply voltage Digital Supply voltage
1)
Parameter
Values 0 to 3.3 0 to 3.3
Unit V V V mA C KV
1) 1)
Digital buffer Supply voltage Digital output current Storage temperature Electrical Static Discharge - HBM - CDM-JEDEC Standard
0 to 3.3 -100 to 100 +150 2 1.5
1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V
OPERATING CONDITIONS
Symbol AVCC DVCC VCCB VREFP VREFM Parameter Analog Supply voltage Digital Supply voltage Digital buffer Supply voltage Forced top reference voltage Forced bottom reference voltage Test conditions Min 2.25 2.25 2.25 1.16 0 Typ 2.5 2.5 2.5 0 Max 2.7 2.7 2.7 AVCC 0.5 Unit V V V V
BLOCK DIAGRAM
+2.5V
VREFP
GNDA VIN INCM VINB stage 1 stage 2 stage n Reference circuit IPOL VREFM
Sequencer-phase shifting CLK
DFSB OEB
Timing
Digital data correction DR DO TO D9 OR GND
Buffers
2/19
TSA1002
PIN CONNECTIONS (top view)
AGND
AVCC
VCCB
GNDB
AVCC
DFSB
VCCB
OEB
NC
NC
NC
DR
index corner
48 1 2 3 4 5 6 7 8 9 10 11 12 13
47 46
45
44 43
42
41
40
39
38 37 36 NC 35 NC 34 NC 33 D0 (LSB) 32 D1 31 D2
IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC
TSA1002
30 D3 29 D4 28 D5 27 D6 26 D7 25 D8
14 15
16
17
18 19
20
21
22
23
24
DGND
DVCC
DVCC
DGND
CLK
DGND
NC
GNDB
GNDB
VCCB
OR
D9 (MSB)
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC DVCC DVCC DGND CLK DGND NC DGND GNDB GNDB VCCB OR Description Analog bias current input Top voltage reference Bottom voltage reference Analog ground Analog input Analog ground Inverted analog input Analog ground Input common mode Analog ground Analog power supply Analog power supply Digital power supply Digital power supply Digital ground Clock input Digital ground Non connected Digital ground Digital buffer ground Digital buffer ground Digital buffer power supply Out Of Range output 0V 0V 0V 2.5V CMOS output (2.5V) CMOS output (2.5V) 1V 0V 0V 1Vpp 0V 1Vpp 0V 0.5V 0V 2.5V 2.5V 2.5V 2.5V 0V 2.5V compatible CMOS input 0V Observation Pin No 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB) NC NC NC NC DR VCCB GNDB VCCB NC NC OEB DFSB AVCC AVCC AGND Description Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Least Significant Bit output Non connected Non connected Non connected Non connected Data Ready output Digital Buffer power supply Digital Buffer ground Digital Buffer power supply Non connected Non connected Output Enable input Data Format Select input Analog power supply Analog power supply Analog ground 2.5V compatible CMOS input 2.5V compatible CMOS input 2.5V 2.5V 0V CMOS output (2.5V) 2.5V 0V 2.5V Observation CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V)
D9(MSB) Most Significant Bit output
3/19
TSA1002
ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25C (unless otherwise specified) TIMING CHARACTERISTICS
Symbol FS DC TC1 TC2 Tod Tpd Ton Toff Parameter Sampling Frequency Clock Duty Cycle Clock pulse width (high) Clock pulse width (low) Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Data Pipeline delay Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state Test conditions Min 0.5 45 9 9 50 10 10 5 6.5 1 1 Typ Max 50 55 Unit Msps % ns ns ns cycles ns ns
TIMING DIAGRAM
N+4 N+3 N+5 N+6
N+2 N-1 N N+1
N+7 N+8
CLK
6.5 clk cycles OEB Tod Toff N-7 N-6 N-5 N-4 N-3 N-2 N Ton N+1
DATA OUT
N-8
DR
HZ state
4/19
TSA1002
CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25C (unless otherwise specified) ANALOG INPUTS
Symbol Parameter Test conditions Min Typ 2.0 7.0 Vin@ Full scale, FS=50Msps
1)
Max
Unit Vpp pF MHz MHz
VIN-VINB Full scale reference voltage Cin BW ERB Input capacitance Analog Input Bandwidth Effective Resolution Bandwidth
100 60
1) See parameters definition for more information
REFERENCE VOLTAGE
Symbol VREFP Parameter Top internal reference voltage Test conditions Min 0.91 Tmin= -40C to Tmax= 85C1) 0.88 1.20 Vpol Ipol Ipol VINCM Analog bias voltage Analog bias current Analog bias current Input common mode voltage Normal operating mode Shutdown mode 0.47 Tmin= -40C to Tmax= 85C1) 0.46 Tmin= -40C to Tmax= 85C
1)
Typ 1.03
Max 1.14 1.16
Unit V V V V A A
1.27
1.35 1.36
1.18 50 70 0 0.57
100
0.68 0.66
V V
1) Not fully tested over the temperature range. Guaranted by sampling.
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TSA1002
CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25C (unless otherwise specified) POWER CONSUMPTION
Symbol ICCA Parameter
1)
Test conditions
Min
Typ 15.6
Max 18 21
Unit mA mA mA mA mA mA A mW mW mW C/W
Analog Supply current Tmin= -40C to Tmax= 85C2)
1)
1.3
2)
2 2
ICCD
Digital Supply Current
1)
Tmin= -40C to Tmax= 85C ICCB Digital Buffer Supply Current Digital Buffer Supply Current in High Impedance Mode Power consumption in normal operation mode Power consumption in High Impedance mode Junction-ambient thermal resistor (TQFP48)
2.5
5 5
Tmin= -40C to Tmax= 85C2)
1)
ICCBZ
40 48
2)
100 60 62
1)
Pd
Tmin= -40C to Tmax= 85C
1)
PdZ Rthja
43 80
48
1) Rpol= 18K. Equivalent load: Rload= 470 and Cload= 6pF 2) Not fully tested over the temperature range. Guaranted by sampling.
DIGITAL INPUTS AND OUTPUTS
Symbol Digital inputs VIL VIH Logic "0" voltage Logic "1" voltage 2.0 0.8 V V Parameter Test conditions Min Typ Max Unit
Digital Outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage Iol=10A Ioh=-10A 2.4 -1.5 1.5 15 0.4 V V A pF
High Impedance leakage current OEB set to VIH Output Load Capacitance
ACCURACY
Symbol OE DNL INL 6/19 Parameter Offset Error Differential Non Linearity Integral Non Linearity Monotonicity and no missing codes Test conditions
Fin= 2MHz, VIN@+1dBFS Fin= 2MHz, VIN@+1dBFS Fin= 2MHz, VIN@+1dBFS
Min -5 -0.7 -0.8
Typ 0.2 0.2 0.3
Max +5 +0.7 +0.8
Unit % LSB LSB
Guaranted
TSA1002
CONDITIONS AVCC = DVCC = 2.5V, Fs= 40Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25C (unless otherwise specified) DYNAMIC CHARACTERISTICS
Symbol Parameter Test conditions Fin= 5MHz Fin= 10MHz Fin= 24MHz SFDR Spurious Free Dynamic Range Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz SNR Signal to Noise Ratio Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz THD Total Harmonic Distortion Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz ENOB Effective Number of Bits Fin= 5MHz Fin= 10MHz Fin= 24MHz
2) 1) 2) 1) 2) 1) 2) 1) 2) 1)
Min 65.5 68.5 63.4 60 60 60 58.5 58.3 57.4 48 48 48 63.5 67.4 62.5 57 55 57 58.5 58.2 57.0 48 48 48 9.6 9.5 9.3 7.9 7.9 7.9
Typ 79.2 77 69
Max
Unit
dBc
dBc
59.5 59.4 59.0 dB
dB
77.8 76 68.1 dB
dB
59.4 59.3 58.5 dB
SINAD
Signal to Noise and DistortionRatio
dB
9.76 9.71 9.60 bits
bits
1) Rpol= 18K. Equivalent load: Rload= 470 and Cload= 6pF 2) Tmin= -40C to Tmax= 85C. Not fully tested over the temperature range. Guaranted by sampling.
7/19
TSA1002
DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 40Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 40Msps. Spurious Free Dynamic Range (SFDR) The ratio between the amplitude of fundamental tone (signal power) and the power of the worst spurious signal (not always an harmonic) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distorsion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD= 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between time when the analog input is initially sampled and time when the corresponding digital data output is valid on the output bus. Also called data latency. It is expressed as a number of clock cycles.
8/19
TSA1002
EQUIVALENT CIRCUITS Figure 1 : Analog Input Circuit
A VCC=2.5V
Figure 3 : Input buffers
VCCbuf=2.5V
VIN
355.5
278.5 208.2
DFS
(or VINB)
P AD CAP ACITANCE
7 pF
7 pF
Req # 33 k
(if Fs=50 MHz)
P AD CAP ANCE ACIT
AGND=0V
com mon m ode
G buff=0V ND
Figure 2 : Input clock circuit
DVC C=2.5V
Figure 4 : Tri-state output buffers
VCC buf=2.5V
CLK
OE
DATA
GND buff=0V VCC buf =2.5V
OUT
2 mA OUTPUT BUFFER
P AD C ACITANCE AP
7 pF
PAD CAPACITANCE 7pF
DGND=0V
GND buff=0V
9/19
TSA1002
Static parameter: Integral Non Linearity Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts
0 .8 0 .6 0 .4
INL (LSBs)
0 .2 0 - 0 .2 - 0 .4 - 0 .6 - 0 .8
0
200
400
600
800
1000
O u tp u t C o d e
Static parameter: Differential Non Linearity Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts
0 .5 0 .4 0 .3 0 .2 0 .1 0 -0 .1 -0 .2 -0 .3 -0 .4 -0 .5 0 200 400 600 800 1000
DNL (LSBs)
O u tp u t C o d e
Linearity vs. AVcc Fs=50MSPS; Icca=20mA; Fin=1MHz
60 10
Distortion vs. AVcc Fs=50MSPS; Icca=20mA; Fin=1MHz
-69
Dynamic parameters (dB)
59.5 59 58.5 58 57.5 57 56.5 56 55.5 55 2.25 2.35 2.45 2.55 2.65 ENOB SINAD SNR
Dynamic Parameters (dB)
9.9
-71 -73 -75 -77 -79 -81 -83 -85 2.25 THD SFDR
9.7 9.6 9.5 9.4 9.3
ENOB (bits)
9.8
2.35
2.45
2.55
2.65
AVCC (V)
AVCC (V)
10/19
TSA1002
Linearity vs. DVcc Fs=50MSPS; Icca=20mA; Fin=1MHz Distortion vs. DVcc Fs=50MSPS; Icca=20mA; Fin=1MHz
59.1
9.6
-65
Dynamic parameters (dB)
Dynamic parameters (dB)
-67 -69 -71 -73 -75 -77 -79 -81 -83 -85 2.25 2.35 2.45 2.55 2.65 THD SFDR
59.05 59
SNR
9.595 9.59
ENOB 58.95 58.9 58.85 58.8 2.25 SINAD 9.585 9.58 9.575 9.57 2.35 2.45 2.55 2.65
DVCC (V)
ENOB (bits)
DVCC (V)
Linearity vs. VccB Fs=50MSPS; Icca=20mA; Fin=1MHz
Distortion vs. VccB Fs=50MSPS; Icca=20mA; Fin=1MHz
59.5
10
-72
Dynamic parameters (dB)
Dynamic Parameters (dB)
59 58.5 58 57.5 57 2.25
SNR
9.9 9.8
-73 -74 -75 -76 -77 -78 -79 -80 2.25 SFDR THD
SINAD 9.7 ENOB 9.6 9.5 9.4 2.35 2.45 2.55 2.65
ENOB (bits)
2.35
2.45
2.55
2.65
VCCB (V)
VCCB (V)
Linearity vs. Fs Icca=20mA; Fin=5MHz
Distortion vs. Fs Icca=20mA; Fin=5MHz
10
-50
Dynamic parameters (dB)
ENOB
Dynamic parameters (dB)
66
-55 -60 -65 -70 -75 -80 -85 -90 25 35 45 55 65 75 SFDR THD
9.5 SNR SINAD ENOB (bits)
61
9 8.5
56
51
8 7.5
46 25 35 45 55 65 75
Fs (MHz)
Fs (MHz)
11/19
TSA1002
Linearity vs. Fs Icca=20mA; Fin=15MHz Distortion vs. Fs Icca=20mA; Fin=15MHz
10
-50
Dynamic parameters (dB)
Dynamic parameters (dB)
66
ENOB
-55 -60 -65 -70 -75 -80 -85 -90 25 35 45 55 65 75
9.5 ENOB (bits)
61
SNR SINAD
9 8.5
THD
56
SFDR
51
8 7.5 25 35 45 55 65 75
46
Fs (MHz)
Fs (MHz)
Linearity vs. Fin Fs=50MSPS; Icca=20mA
Distortion vs. Fin Fs=50MSPS; Icca=20mA
-50
Dynamic parameters (dB)
64 9.6 62 60 SNR 58 56 54 0 20 40 60 8.6 ENOB 9.1
Dynamic parameters (dB)
-55 -60 -65 -70 -75 -80 -85 0 20 40 60 THD SFDR
SINAD
8.1
7.6
Fin (MHz)
ENOB (bits)
Fin (MHz)
Linearity vs.Temperature Fs=50MSPS; Icca=20mA; Fin=5MHz
Distortion vs. Temperature Fs=50MSPS; Icca=20mA; Fin=5MHz;
Dynamic Parameters (dB)
62 60 58 56 54 52 50 -50 0
ENOB SNR
Dynamic Parameters (dB)
64
SINAD
10 9.8 9.6 9.4 9.2 9 8.8 8.6 8.4 8.2 8
80
75 SFDR 70 THD
65
60
55 -50 0 50 100
50
100
Temperature (C)
Temperature (C)
12/19
TSA1002 APPLICATION NOTE
DETAILED INFORMATION The TSA1002 is a High Speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 9 internal conversion stages in which the analog signal is fed and sequencially converted into digital data. Each 8 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the conversion delay. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) OPERATIONAL MODES DESCRIPTION
Inputs Analog input differential level (VIN-VINB) -RANGE RANGE> (VIN-VINB) -RANGE RANGE> > > (VIN-VINB) > > (VIN-VINB) X RANGE (VIN-VINB) >-RANGE RANGE (VIN-VINB) >-RANGE DFSB H H H L L L X
couple for each stage. The corrected data are outputed through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the Data Ready signal. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA1002 is pin to pin compatible with the 8bits/40Msps TSA0801, the 10bits/25Msps TSA1001 and the 12bits/50Msps TSA1201. This ensures a conformity within the product family and above all, an easy upgrade of the application.
Outputs OEB L L L L L L H OR H H L H H L HZ DR CLK CLK CLK CLK CLK CLK HZ Most Significant Bit (MSB) D9 D9 D9 Complemented D9 Complemented D9 Complemented D9 HZ
Data Format Select (DFSB) When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. This results in
13/19
lower consumption while the converter goes on sampling. When OEB is set to low level again, , the data is then valid on the output with a very short Ton delay. The timing diagram summarizes this operating cycle. Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range.
TSA1002
Typically, there is a detection of all the data being at '0' or all the data being at '1'. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range. Data Ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D9). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As digital output, DR goes in high impedance state when OEB is asserted to High level as described in the timing diagram. DRIVING THE ANALOG INPUT
50
Single-ended input configuration Some applications may require a single-ended input which is easily achieved with the configuration reported on Figure 6. In this case, it is recommended to use an AC-coupled analog input and connect the other analog input to the common mode voltage of the circuit (INCM) so as to properly bias the ADC. The INCM may remain at the same internal level (0.56V) thus driving only a 1Vpp input amplitude, or it must be increased to 0.9V to drive a 2Vpp input amplitude. You will get higher performances using a 2Vpp signal. Figure 6 : Single-ended input configuration
Signal source
100nF
VIN
TSA1002
VINB INCM
Differential inputs The TSA1002 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 5 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.56V. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1 transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp. Figure 5 : Differential input configuration
Analog source ADT1-1 1:1 VIN
50 100pF 330pF
10nF
470nF
0.9V
Dynamic characteristics, while not being as remarkable as for differential configuration, are still of very good quality. Measurements done at 50Msps, 2MHz input frequency, -1dBFS input level sum up these performances. An SFDR of -64.5dBc, a SNR of 57.8dB and an ENOB Full Scale of 9.3bits are achieved. REFERENCE CONNECTION Internal reference In the standard configuration, the ADC is biased with the internal reference voltage. VREFM pin is connected to Analog Ground while VREFP is internally set to a voltage of 1.03V. It is recommended to decouple the VREFP in order to minimize low and high frequency noise. Refer to Figure 7 for the schematics. Figure 7 : Internal reference setting
TSA1002
VINB INCM
VIN
1.03V VREFP
330pF
10nF 470nF
TSA1002
330pF 10nF 470nF
VINB VREFM
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TSA1002
External reference It is possible to use an external reference voltage instead of the internal one for specific applications requiring even better linearity or enhanced temperature behaviour. In this case, the amplitude of the external voltage must be at least equal to the internal one (1.03V). Using the STMicroelectronics Vref TS821 leads to optimum performances when configured as shown on Figure 8. Figure 8 : External reference setting
60 50 RPOL 20 18 16 12 30 20 ICCA 10 0 25 35 45 55 65 75 10 8 6 4 2 0 Rpol (kOhms) 14
The TSA1002 will combine highest performances and lowest consumption at 50Msps when Rpol is in the range of 12k to 20k. At lower sampling frequency, this value of resistor may be changed and the consumption will decrease as well. The figure 9 sums up the relevant data. Figure 9 : Analog Current consumption vs. Fs According value of Rpol polarization resistance
1k VCCA VREFP VIN
TSA1002
VINB VREFM
TS821 external reference
Icca (mA)
330pF
10nF 470nF
40
Fs (MHz)
At 15Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved of up to 2dBc on SFDR and 0.3dB on SINAD. At 50Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved of up to 1dBc on SFDR and 0.6dB on SINAD. This can be very helpful for example for multichannel application to keep a good matching among the sampling frequency range. Clock input The quality of your converter is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The duty cycle must be between 45% and 55%. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5Msps, before applying the supply voltages. Power consumption The internal architecture of the TSA1002 enables to optimize the power consumption according to the sampling frequency of the application. For this purpose, a resistor is placed between IPOL and the analog Ground pins.
Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is mandatory for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output
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TSA1002
capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). EVAL1002 evaluation board The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 10. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: SFSR=+0.2dB for static parameters.SFSR=-0.5dB for dynamic parameters.
Figure 10 : Analog to Digital Converter characterization bench
Power
HP8644B Sine wave Generator
Vin
ADC evaluation board
ck
data
Logic Analyzer
dataready
TLA704 HP8133A Pulse Generator
HP8644B
Sine Wave Generator
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J9 DFSB J11 1 2 1 2 1 2 VCCB2 C34
+
J10 OEB J13 1 2
J17 VDDBUFF3V
R10 47K R11 47K R12 47K R13 47K C16 AVCC 470nF C15 10nF C14 R2 1K 330pF 330pF R14 R15 R16 R17 R18 R19 47K 47K 47K 47K 47K 47K 330pF 10nF C25 10nF C26 DR DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 C38 C29 6 2 4
+
1 2
C28 VCCB1 470nF C27 470nF C39
47 C37
J2 Raj1 47K
1 2
VrefP
J6
J5
1 2
VrefM C32 470nF AGND AVCC AVCC DFSB OEB NC NC 2.5VCCBUFF GNDBUFF 2.5VCCBUFF DR D0 10nF 330pF C31 C13 C12 C30 330pF 470nF 10nF C11 48 47 46 45 44 43 42 41 40 39 38 37
J1 Vin
1
T2
6
2
Figure 11 : TSA1002 Evaluation board schematic
R1 50 3
4 T2-AT1-1WT 8-14bits ADC TSA1002 74LCX573
C1 100pF
1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE
20 19 18 17 16 15 14 13 12 11
J7
C10
C9
C8
1 2 C3 AVCC 470nF 10nF 330pF C4 C2
470nF 10nF
330pF
Regl com mode J8
C7
C6
C5
1 2 13 14 15 16 17 18 19 20 21 22 23 24
Mes com Mode J12 74LCX573
DVCC DVCC DGND CLK DGND NC DGND GNDBUFF GNDBUFF 2.5VCCBUFF OR D13
470nF 10nF
330pF
1 2 3 4 5 6 7 8 9 10 11 12 Ipol VrefP VrefM AGND Vin AGND VINB AGND INCM AGND AVCC AVCC 1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 20 19 18 17 16 15 14 13 12 11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
36 35 34 33 32 31 30 29 28 27 26 25
2 1
AVCC
+
C42 47F
J19 C20 10F C17
C41 10F
OR 470nF C40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32PIN
1 2
AGND
J20 1 330pF C21 3 R3 50 10nF C19 470nF C24 10
+
1 2 10nF C22 470nF C23 10
+
T1 T2-AT1-1WT 330pF C18
10nF C33 330pF
DGND
J21
1 2
GndB2 C36 47 2 1 J4 CLJ/SMB C35 47 VCCB1
J22
1 2 2 1
GndB1 J15 DVCC J16 CON2
J18 VccB1
2 1
TSA1002
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TSA1002
Figure 12 : Printed circuit of evaluation board.
Printed circuit board - List of components
P a rt T yp e 10 u F 10 u F 10 u F 10 u F 10 0 p F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 1K 3 2 P IN 330pF 330pF D e s i g n F o o t p r in t ato r C 24 C 23 C 41 C 29 C1 C 12 C 39 C 15 C 40 C 27 C4 C 21 C 31 C6 C9 C 18 R2 J6 C 25 C 26 12 10 12 10 12 10 12 10 603 603 603 603 603 603 603 603 603 603 603 603 603 ID C 3 2 603 603 P a rt T yp e 3 3 0 pF 3 3 0 pF 3 3 0 pF 3 3 0 pF 3 3 0 pF 3 3 0 pF 3 3 0 pF 3 3 0 pF 3 3 0 pF 47uF 47uF 47uF 47uF 4 7 0 nF 4 7 0 nF 4 7 0 nF 4 7 0 nF 4 7 0 nF 4 7 0 nF 4 7 0 nF D e s ig n F o o t p r in t ato r C 33 C 20 C8 C2 C5 C 11 C 30 C 17 C 14 C 36 C 34 C 35 C 42 C 22 C 32 C 37 C 38 C 13 C 28 C 10 603 603 603 603 603 603 603 603 603 CAP CAP CAP CAP 805 805 805 805 805 805 805 P a rt T yp e 470nF 470nF 470nF 470nF 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 50 50 D e s i g n F o o t p r in t ato r C7 C 16 C 19 C3 R 12 R 14 R 11 R a j1 R 10 R 19 R 13 R 15 R 16 R 17 R 18 R3 R1 805 805 805 805 603 603 603 VR 5 603 603 603 603 603 603 603 603 603 TSSOP 20 TSSOP 20 S IP 2 P a rt T yp e A VC C C LJ / S M B A GN D D FSB D GN D D VC C G ndB 1 G ndB 2 D e s ig n ato r J 12 J4 J 19 J9 J20 J 15 J22 J21 F IC H E 2 M M SM B /H F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M ADT ADT F IC H E 2 M M F IC H E 2 M M SM B /H F IC H E 2 M M F IC H E 2 M M T QF P 48 F o o t p r in t
M es co m m o de J8 OEB J 10
R e gl c o m m o de J 7 T 2 - A T 1- 1W T T 2 - A T 1- 1W T VccB 1 VD D B UF F 3V V in V re f M V re f P T S A 10 0 2 T2 T1 J 18 J 17 J1 J5 J2 U1
7 4 LC X 5 7 3 U3 7 4 LC X 5 7 3 U2 CON2 J 16
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TSA1002
PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE
A A2 48 1 e A1 37 36 0,10 mm .004 inch SEATING PLANE
12 13 24
25
E3 E1 E
D3 D1 D
L1
L
K
Millimeters Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 Typ. Max. 1.60 0.15 1.45 0.27 0.20
0,25 mm .010 inch GAGE PLANE
Min. 0.002 0.053 0.007 0.004
B
c
Inches Typ. Max. 0.063 0.006 0.057 0.011 0.008 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 0.45 0.75 0.018
0.030
0 (min.), 7 (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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